(1) Field of the Invention
The present invention relates to integrated semiconductor fabrication, more particularly to improved methods of fabricating the metallurgy system of semiconductor devices.
(2) Description of the Invention
Microelectronic semiconductor devices and circuits must be made to very exacting specification to assure high electrical operating characteristics and dependable performance. As the circuitry of integrated circuit semiconductor gets more complex and more dense, the number of layers of metallurgy must increase. With the increase in metallurgy layers, the surface planarily of each successive layer becomes more non-planar due to the interlayer insulating layers following the contour of the underlying metallurgy stripes and supporting layer. With each successive layer there are more metallurgy layers to contribute to the irregularity of the surface. Structures with two or more levels can develop severe non-polar topographies, and may face severe reliability problems as the result of poor metal step-coverage and poor microlithographic delineation processes. A potential solution to overcome these problems is a planarization process of the dielectric interlayers. Both inorganic and organic layers deposited by spin-on-glass (SOG) techniques have been widely used for microminiaturized multilevel interconnection circuitry. The deposited dielectric layers have conventionally been subjected to an etch back process which further smoothens the surface. However, this layer etch back step adds an extra step in the process for each layer deposited, which results in added cost and the potential for reducing the yield. It has been discovered that the organic SOG layer can be planarized by heating. This sufficiently smoothens out the surface so that the etch back step is not needed. However, these interlayers have other problems. These layers when subjected to O.sub.2 plasma, used to remove the resist used to form via holes, results in the absorption of H.sub.2 O in the layer which is deleterious to the metallurgy. Further the interlayers are prone to via poisoning problems and the hydrogen effect which may result in field inversion, poly load resistance shifting and generation of hot carriers. For a more in depth discussion see SHUN-LIANG HSU et al "Field Inversion Generated in CMOS Double Metal Process Due to PE TEOS and SOG Interactions" IEEE Transactions on Electron Devices, Vol. 40., No. 1, January 1993, pp. 49-53.
In view of the desirability of organic SOG layers, efforts have been made to cure the aforementioned problems. A paper entitled "An Advanced Interlayer Dielectric System With Partially Converted Organic SOG By Using Plasma Treatment" by Matsuura et al, 1993 VMIC Conference, 1993 ISMIC--102/93/0113, describes treating organic SOG films with a N.sub.2 plasma. The treatment is described as capable of dehydrating the film.